TSIA Recent Advances and New Trends in 3D IC Integration
2013-06-07 ~ 2013-06-08
報名費用(Registration fee):
會員報名費用: 5000
非會員報名費用: 6500
幣別: 新台幣(NTD)
聯絡窗口(Contact Window):
電話: 03-5913181
傳真: 03-5820056
Email: candy@tsia.org.tw


3D integration consists of 3D IC packaging, 3D IC integration, and 3D Si integration, which will be discussed in this lecture. Emphases are placed on the key enabling technologies for 3D IC integrations, such as TSV (through-silicon via) forming and filling, front and back-side metallization, RDL (redistribution layer), temporary wafer bonding, wafer thinning and handling, wafer de-bonding, thin chip/wafer strength measurement and improving, lost-cost lead-free microbumping and assembly, C2C, C2W, and W2W bonding, and thermal management. Useful characterization and reliability data for 3D IC integration will also be provided. The application of 3D IC integration such as MEMS, LED, logic + logic, memory + microprocessor, wide I/O DRAM, active and passive interposers will be presented. Furthermore, the critical issues of TSV and 3D IC integration will be given and some potential solutions or research topics will be recommended. Finally, the supply chains for high volume manufacturing of 3D IC integration will be discussed and several roadmaps of 3D IC integration will be provided. All the materials are based on the technical papers and books published within the past 3 years by the lecturer and others.

2.Overview and outlook of 3D IC packaging
3.Overview and outlook of 3D Si integration
4.Overview and outlook of 3D IC integration
5.Potential applications of 3D IC integration
   Memory-chip stacking
   Wide I/O Memory
   Wide I/O DRAM
   Wide I/O interface
6.TSV forming (DRIE and laser)
7.TSV dielectric, barrier, and seed-metal layers deposition
8.TSV filling and CMP
9.TSV Cu revealing
10.2.5D interposers
   Used as intermediate substrate
   Used as stress relief (reliability) beffer
   Used as carrier
   Used as thermal management tool
11.3D IC integration with interposers
12.Stress sensor for thin-chip strength measurement
13.Wafer thinning and thin-wafer handling
14.Low-cost lead-free microbumps (≤15µm pitch): fabrication and characterization
15.Low-cost lead-free microbumps (≤15µm pitch): assembly and reliability
16.C2C, C2W, and W2W bonding
17.3D IC chip stacking with low temperature bonding
18.3D MEMS and IC integration
19.3D LED and IC integration
20.Equivalent thermal conductivities for copper-filled TSV interposer/chip
21.Thermal management (design charts and guidelines) for 3D stacked chips
22.Integrated liquid cooling solutions for 3D IC stacked modules
23.Hot spots in thin chips for 3D IC stacking
24.Embedded 3D hybrid IC Integration SiP With TSV for Opto-Electronic Interconnects
25.Supply chain for 3D IC integration 
26.Critical issues in adopting TSV and 3D IC integration
27.Some 3D IC/Si integration roadmaps

講  師: 劉漢誠(John Lau)
學經歷: Dr. John Lau has been an ITRI Fellow of Industrial Technology Research Institute (ITRI in Taiwan) since January 2010. Prior to that, he was a visiting professor at HKUST for 1 year, the Director of MMC Laboratory with IME in Singapore for 2 years and a Senior Scientist/MTS at HPL/Agilent in California, US for more than 25 years. With more than 35 years of R&D and manufacturing experience, he has published more than 350 peer-reviewed papers, 30 issued and pending US patents, given 270 lectures/workshops/keynotes worldwide, published 17 textbooks on TSV for 3D integrations, 3D MEMS packaging, flip chip & WLP, high-density PCB, SMT, and lead-free materials, soldering, manufacturing and reliability. John earned his PhD degree from the University of Illinois, 3 MASc degrees in North America. John received many awards and is an elected ASME Fellow and has been an IEEE Fellow since 1994.
專  長: 3D IC integration

課程時間:2013/6/7~6/8,6/7(週五)晚間18:00-22:00,6/8 (週六)日間8:30-17:30,共計12小時。